This invention relates generally to high voltage transistors and more particularly concerns a high voltage electrically stackable NMOS transistor which is fabricated with a "star" shaped field plate that is also a high value high voltage resistor which facilitates electrical stacking of several transistors and thus extend the voltage range for the circuit.
This invention also relates to configurations of field plates that provide the greatest breakdown voltages with the highest ohmic values.
NMOS transistors are lateral devices. In high voltage applications, the transistor is designed to withstand high voltages by constructing a field plate between the gate and drain regions. The field plates space out the equipotential field lines to avoid voltage concentrations. To increase the voltage range of the circuit, it is common to stack several devices in a series configuration. However, when electrically stacking several transistors together, high voltage resistors are needed to set the correct bias potentials at the gates of the several devices. In discrete forms, high voltage components, including high voltage resistors, are very bulky. Even in integrated forms, high voltage resistors are very large. Therefore a large area of silicon is needed to accommodate the high voltage resistors when integrated with high voltage transistors. High voltage devices can be conventionally integrated using well know integrated device processes.
FIG. 1 shows a planar view looking down on a conventional high voltage NMOS device 10. While the preferred embodiment of this device is circular, any annular configuration may be used, for example ellipses. However, it is preferable to avoid geometries with sharp or angular corners. The center of the conventional high voltage NMOS device 10 is a drain area 12. Adjacent to and outside of the drain area 12 is a spiral field plate 14. The spiral field plate 14 is made from polysilicon, which has a high resistance. Adjacent to and outside of the spiral field plate 14 is a gate 16. Adjacent to and outside of the gate 16 is a source area 18. Providing an electronic connection between the drain area 12 and the spiral field plate 14 is a metal drain/field plate connector 13. Providing a connection between the spiral field plate 14 and the gate area 16 is a metal gate/field plate connector 15.
FIG. 2 shows a partial cross-section of the high voltage NMOS device 10. Only a partial cross-section is shown since the device is symmetrical across centerline C1. The drain area 12 surrounds the centerline C1. Outside of and adjacent to the drain area 12 is the spiral field plate 14. Providing an electrical connection between the spiral field plate 14 and the drain area 12 is the drain/field plate connector 13. Outside of the spiral field plate 14 is the gate area 17. Providing an electrical connection between the spiral field plate 14 and the gate 16 is the gate/field plate connector 15. Outside of and adjacent to the gate area 17 is the source area 18.
FIG. 3 shows a schematic of the conventional high voltage NMOS device 10. Identical elements are labeled with the same identifying numbers used in FIG. 1. The drain area 12, gate area 16, and source area 18 are the basic components of the conventional high voltage NMOS device 10. The spiral field plate 14 is represented as a resistor connected between the drain area 12 and the gate 16. Alternatively, the spiral field plate 14 could be connected between the drain area 12 and the source area 18 as shown in FIG. 4.
In some high voltage applications, conventional high voltage NMOS devices 10 are cascaded to extend the voltage range of the resultant device. Such a cascaded electrical series network is shown in FIG. 5 and contains four conventional high voltage NMOS devices 20, 22, 24, 26, although it could be comprised of any number of conventional high voltage NMOS devices. The four high voltage NMOS devices 20, 22, 24, 26 are connected in parallel across a voltage divider network comprised of four resistors 28, 30, 32, 33. Resistor 28 is connected between the gate terminals 34, 36 of high voltage NMOS device 20 and high voltage NMOS device 22. Resistor 30 is connected between the gate terminals 36, 38 of high voltage NMOS device 22 and high voltage NMOS device 24. Resistor 32 is connected between the gate terminals 38, 40 of high voltage NMOS device 24 and high voltage NMOS device 26. Resistor 33 is connected between the gate terminal of high voltage NMOS device 20 and the drain of high voltage NMOS device 20. In order to function properly, the resistors 28, 30, 32, 33 must be constructed as large, high voltage resistors which consume a large part of silicon wafer real estate.
Accordingly, it is the primary aim of the invention to provide a high current, high voltage transistor which can be easily electrically stacked to extend the voltage range of the resultant circuit and uses less silicon area than a conventional electrically stacked transistor configuration.
Another aim of this invention is to provide a configuration of field plates that provide the greatest breakdown voltages with the highest ohmic values.
Further advantages of the invention will become apparent as the following description proceeds.